データシート | | |
| | TMS320C6746-300 | | CPU | 1 C674x | | Peak MMACS | 2400 | | Frequency(MHz) | 300 | | On-Chip L1/SRAM | 64 KB | | On-Chip L2/SRAM | 256 KB | | ROM | 1024 KB | | EMIF | 1 16-Bit EMIFA,16-Bit DDR2/mDDR | | External Memory Type Supported | Async SRAM,SDRAM,DDR2,mDDR,NAND Flash,NOR | | DMA | 2 32-Ch EDMA | | EMAC | 10/100 | | HPI | 1 16-bit | | uPP | 1 | | VPIF | 1 | | MMC/SD | 2 | | I2C | 2 | | SPI | 2 | | UART | 3 | | USB | 1 | | PWM | 2 | | eCAP | 3 | | McASP | 1 | | McBSP | 2 | | Timers | 3 64-Bit GP,1 64-Bit GP/WD | | RTC | 1 | | Core Supply (Volts) | 1.2 V,1.1 V,1.0 V,(Variable) | | IO Supply (Volts) | 1.8 V,3.3 V | | Operating Temperature Range (°C) | 0 to 90,-40 to 105 | | | サンプル | | | 在庫がありません |
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製品情報
特長 - 300-MHz C674x VLIW DSP
- C674x Instruction Set Features
- Superset of the C67x+™ and C64x+™ ISAs
- 2400/1800 C674x MIPS/MFLOPS
- Byte-Addressable (8-/16-/32-/64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- Compact 16-Bit Instructions
- C674x Two Level Cache Memory Architecture
- 32K-Byte L1P Program RAM/Cache
- 32K-Byte L1D Data RAM/Cache
- 256K-Byte L2 Unified Mapped RAM/Cache
- Flexible RAM/Cache Partition (L1 and L2)
- 1024K-Byte Boot ROM
- Enhanced Direct-Memory-Access Controller 3 (EDMA3):
- 2 Channel Controllers
- 3 Transfer Controllers
- 64 Independent DMA Channels
- 16 Quick DMA Channels
データシートを開いて、すべての特長を表示
概要 The device is a Low-power applications processor based on a C674x DSP core. It provides significantly lower power than other members of the TMS320C6000™ platform of DSPs. The device enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution. The device DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256KB memory space that is shared between program and data space. データシートを開いて、すべての概要を表示
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