データシート
CDCE62002 CDCE62005 CDCM61004 VCC(V) 3.3 3.3 3.3 Input Level LVPECL,LVDS,LVCMOS LVPECL,LVDS,LVCMOS Crystal or LVCMOS Output Level LVPECL,LVDS,LVCMOS LVPECL,LVDS,LVCMOS LVPECL or LVDS or 2 LVCMOS No. of Outputs 2 5 4 Output Frequency(Min)(Mhz) 10.94 4.25 43.75 Output Frequency(Max)(Mhz) 1175 1175 683.28 Divider Ratio Universal Universal Universal RMS Jitter 1ps 500fs Typical, <1ps Max Operating Frequency Range(Min)(MHz) 10.94 4.25 43.75 Operating Frequency Range(Max)(MHz) 1175 1175 683.28 Output Skew(ps) 75 75 Voltage Range 3.3 3.3 3.3 Supply Current(mA) 230 108mA Max サンプル サンプル サンプル 在庫 在庫 在庫
この製品をチェックした人は次の製品もチェックしています
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OPA227 : 超高精度、低雑音オペアンプ
CDCM7005 : 高性能、低位相雑音、低スキュー・クロック・シンセサイザ、基準クロック/VCXO 同期
製品情報 特長
Frequency Synthesizer With PLL/VCO and Partially Integrated Loop Filter Fully Configurable Outputs Including Frequency and Output Format Smart Input Multiplexer Automatically Switches Between one of two Reference Inputs. Multiple Operational Modes Include Clock Generation via Crystal, SERDES Startup Mode, Jitter Cleaning, and Oscillator Based Holdover Mode. Integrated EEPROM Determines Device Configuration at Power-up. Excellent Jitter Performance Integrated Frequency Synthesizer Including PLL, Multiple VCOs, and Loop Filter: Full Programmability Facilitates Phase Noise Performance Optimization Enabling Jitter Cleaner Mode Programmable Charge Pump Gain and Loop Filter Settings Unique Dual-VCO Architecture Supports a Wide Tuning Range 1.750 GHz – 2.356 GHz. Universal Output Blocks Support up to 2 Differential, 4 Single-Ended, or Combinations of Differential or Single-Ended: 0.5 ps RMS (10 kHz to 20 MHz) Output Jitter Performance Low Output Phase Noise: –130 dBc/Hz at 1 MHz offset, Fc = 491.52 MHz Output Frequency Ranges From 10.94 MHz to 1.175 GHz in Synthesizer Mode LVPECL, LVDS and LVCMOS Independent Output Dividers Support Divide Ratios for 1,2,3,4,5,8,10,12,16,20,24 and 32.
Flexible Inputs With Innovative Smart Multiplexer Feature: Two Universal Differential Inputs Accept Frequencies from 1 MHz up to 500 MHz (LVPECL), 500 MHz (LVDS), or 250 MHz (LVCMOS). One Auxiliary Input Accepts Crystals in the Range of 2MHz–42MHz Clock Generator Mode Using Crystal Input データシートを開いて、すべての特長を表示
概要
The CDCE62002 is a high performance clock generator featuring low output jitter, a high degree of configurability via a SPI interface, and programmable start up modes determined by on-chip EEPROM. Specifically tailored for clocking data converters and high-speed digital signals, the CDCE62002 achieves jitter performance under 0.5 ps RMS10 kHz to 20 MHz integration bandwidth.. It incorporates a synthesizer block with partially integrated loop filter, a clock distribution block including programmable output formats, and an input block featuring an innovative smart multiplexer. The clock distribution block includes two individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS).
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サンプルおよび注文カート 
